An SOC is generally an integrated circuit (IC) that integrates multiple components of a computer or other electronic system onto a single chip. Often, SOCs will contain multiple processing units designed for application-specific processing tasks. Generally, SOCs may consume less power, less space, and have a higher reliability than a multi-chip system they replace. As a result, SOCs are often included in computer and/or electronic devices, particularly portable devices.
Designing an SOC is a complex and time-consuming process. Generally, a high-level design description of the processing units and other function blocks of the SOC are created in C programing language, SystemC, or the like. Hardware synthesis may be employed to automatically synthesize a hardware description from the high-level design description. The processing units are designed in a high-level design description and are synthesized into a hardware description. Use of high-level synthesis may generally reduce the design cost of the processing units and other functional blocks compared to designing the hardware directly.
Conversely, interconnects between the processing units, functional blocks, and the like are generally designed using lower level descriptions, such as HDL, rather than high level descriptions that may be used in designing the processing units as described above. These interconnects are generally designed as a bus system that includes various interconnect bus protocols. As a result, all of the processing units in such a system are generally designed to comply with interconnect bus protocols. The path data travels to and from processing units and/or memory locations may be relatively complex due to the bus system and the bus protocols. For example, a piece of data may be moved among processing units and other functional blocks through a series of commands from a direct memory access (DMA) controller. Generally, these bus systems cause data communication by the processing units to represent a first in, first out (FIFO) data stream. Additionally, these bus systems, bus protocols, and interconnections are typically relatively complex. The processing units are designed to comply with a complex bus protocol to communicate data via the interconnect system.
After the processing units and the interconnect system are designed and the processing units are synthesized into a hardware description, the SOC design is functionally verified. Functional verification may take place in specialized, expensive acceleration and/or emulation boxes, or may also be performed via field-programmable gate array (FPGA) prototypes or the like. During functional verification, errors and/or design bugs may be identified. The high-level design description may then be revised in light of the identified errors and/or bugs, resynthesized, and again functionally verified. This iterative process may be repeated until the functional verification is successful. Once the complete SOC design is functionally verified, the SOC may be produced according to the final design.
The subject matter claimed herein is not limited to embodiments that solve any disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one example technology area where some embodiments described herein may be practiced.